PHASE DETECTOR AND PHASE DIFFERENCE COMPENSATING METHOD
PROBLEM TO BE SOLVED: To provide a phase detector for delay locked loop to be exactly operated whenever a master reset signal is activated (namely whenever a delay locked loop is operated). SOLUTION: The phase detector has D flip-flops 110 and 120 for generating phase difference detecting signals UP...
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a phase detector for delay locked loop to be exactly operated whenever a master reset signal is activated (namely whenever a delay locked loop is operated). SOLUTION: The phase detector has D flip-flops 110 and 120 for generating phase difference detecting signals UP and DOWN, an initial status setting logic 140 for generating first and second initial status setting signals INTL1 and INTL2 and a reset control logic 130 for generating independent separated first and second reset signals A2 and A3 in accordance with the combination of the phase difference detecting signals and the initial status setting signals. Before a master reset signal RESETB is activated, according to the phase relationship of a reference clock signal REFCLK and a feedback clock signal FBCLK, the respective statuses of the phase difference detecting signals UP and DOWN are preset. COPYRIGHT: (C)2003,JPO |
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