SEMICONDUCTOR MEMORY DEVICE AND ITS TEST METHOD

SEMICONDUCTOR MEMORY DEVICE AND ITS TEST METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its test method. SOLUTION: The semiconductor memory device adopts a power supply system in which power supply voltage supplied to a cell region is separated from power supply voltage supplied to a peripheral circuit region. Especiall...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NAM HYOU-YOUN, HAN GONG-HEUM, KWAK CHOONG-KEUN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TESTING
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its test method. SOLUTION: The semiconductor memory device adopts a power supply system in which power supply voltage supplied to a cell region is separated from power supply voltage supplied to a peripheral circuit region. Especially, during wafer burn-in test operation mode, power supply voltage applied to the cell region is higher than power supply voltage applied to the peripheral circuit region. If a wafer burn-in test operation is performed under such power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be surely cut off. COPYRIGHT: (C)2003,JPO