PLL CIRCUIT

PROBLEM TO BE SOLVED: To suppress a wander and a jitter without a phase ripple of output clock by enabling the frequency at look to be maintained even if abnormality such as break, etc., occurs in an input clock. SOLUTION: A fundamental circuit for phase preservation is composed of a phase comparator 1, a low-pass filter 3, a voltage control oscillator 4, and a frequency divider 12. An abnormality detector 10 monitors the pulse width of a phase error signal (c), and judges it to be in abnormal state when it gets over a specified threshold such as the time of break of an input clock, etc. At this time, a controller 11 controls a selector 13 to selectively output a phase error signal (f) stored in a phase error holder 2 to the low-pass filter 3, thus it can keep the lock state where the frequency is stable by suppressing the wander and the jitter.