SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To reduce leak current while an internal circuit holds data during sleep mode even when the power supply voltage used in the sleep mode is lowered. SOLUTION: The semiconductor integrated circuit is provided with a voltage- drop circuit 2 which gives a voltage dropped from the v...

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Bibliographische Detailangaben
Hauptverfasser: MAKINO HIROYUKI, NOTANI HIROMI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce leak current while an internal circuit holds data during sleep mode even when the power supply voltage used in the sleep mode is lowered. SOLUTION: The semiconductor integrated circuit is provided with a voltage- drop circuit 2 which gives a voltage dropped from the voltage of power supply line VA2 to the power supply line VA1 in place of the voltage supplied when a switch QA1 turns ON during the sleep mode, a power supply line GND in which the voltage is fixed to the ground potential, and a charge pump circuit 10 which outputs the ground voltage during the active mode but outputs a voltage which is lower than the ground potential during the sleep mode. The source electrodes of the pMOS transistors Q3, Q4 of the internal circuit 1 (latch circuit) are connected to the power supply line VA1, and substrate electrodes are connected to the power supply line VA2. The source electrodes of the nMOS transistors Q5, Q6 of the internal circuit 1 are connected to the power supply line GND, and a voltage outputted from the charge pump circuit is applied to the substrate electrodes.