CHIP-STACKED PACKAGE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a chip-stacked package device composed of stacked semiconductor IC devices of the same size and its manufacturing method. SOLUTION: A chip-stacked package device 100 is equipped with a board 10 provided with a mounting surface 12 and an undersurface 13, a lower semic...

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Bibliographische Detailangaben
Hauptverfasser: KYO SHIIN, OH SE YONG, KWON YONG-HWAN
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a chip-stacked package device composed of stacked semiconductor IC devices of the same size and its manufacturing method. SOLUTION: A chip-stacked package device 100 is equipped with a board 10 provided with a mounting surface 12 and an undersurface 13, a lower semiconductor chip 20, and an upper semiconductor chip 30. The lower semiconductor chip 20 is provided with a top surface and an undersurface, the undersurface of the semiconductor chip 20 is pasted on the mounting surface 12 of the board 10, and a plurality of electrode pads 24 are formed on the top surface. The upper semiconductor chip 30 is provided with a top surface and an undersurface, the undersurface is pasted on the top surface of the lower semiconductor chip 20, and electrode pads 34 are formed on the top surface of the upper semiconductor chip 30, and trenches 35 are formed on the undersurface at positions corresponding to the electrode pads 24 of the top surface of the lower electrode.