METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To prevent disconnection and peel-off of wiring constituting a semiconductor integrated circuit device, a bit line of a DRAM for instance. SOLUTION: An HDP silicon oxide film 34 is deposited by a high density plasma CVD method on the bit line BL connected with a source/drain re...

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Hauptverfasser: HOSHINO YOSHINORI, FUJIWARA TAKESHI, ASAKA KATSUYUKI, NARIYOSHI YASUHIRO, OMORI KAZUTOSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent disconnection and peel-off of wiring constituting a semiconductor integrated circuit device, a bit line of a DRAM for instance. SOLUTION: An HDP silicon oxide film 34 is deposited by a high density plasma CVD method on the bit line BL connected with a source/drain region (17) of a MISFET for memory cell selection of a DRAM memory cell, RTA(heat treatment) is executed at 750 deg.C, then the surface is polished and a capacitor C connected with the other source/drain region (17) of the MISFET for the memory cell selection is formed thereafter. As a result, even when the heat treatment for crystallizing a capacitive insulating tantalum oxide film constituting the capacitor C is performed, film stress applied to the bit line BL is reduced and the disconnection and peel-off of the bit line BL are prevented.