FEOL CAPACITOR AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor....

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: OKORN-SCHMIDT HARALD F, BUCHANAN DOUGLAS A, BALLANTINE ARNE W, CARTIER EDUARD A, COOLBAUGH DOUGLAS D, GOUSEV EVGENI P
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator OKORN-SCHMIDT HARALD F
BUCHANAN DOUGLAS A
BALLANTINE ARNE W
CARTIER EDUARD A
COOLBAUGH DOUGLAS D
GOUSEV EVGENI P
description PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor. SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2003051549A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2003051549A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2003051549A3</originalsourceid><addsrcrecordid>eNrjZNB2c_X3UXB2DHB09gzxD1Jw9HNR8AwJVvB19At1c3QOCQ3y9HNX8HUN8fB34WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGxgamhqYmlo7GRCkCAKo1JTQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FEOL CAPACITOR AND ITS MANUFACTURING METHOD</title><source>esp@cenet</source><creator>OKORN-SCHMIDT HARALD F ; BUCHANAN DOUGLAS A ; BALLANTINE ARNE W ; CARTIER EDUARD A ; COOLBAUGH DOUGLAS D ; GOUSEV EVGENI P</creator><creatorcontrib>OKORN-SCHMIDT HARALD F ; BUCHANAN DOUGLAS A ; BALLANTINE ARNE W ; CARTIER EDUARD A ; COOLBAUGH DOUGLAS D ; GOUSEV EVGENI P</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor. SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030221&amp;DB=EPODOC&amp;CC=JP&amp;NR=2003051549A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030221&amp;DB=EPODOC&amp;CC=JP&amp;NR=2003051549A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OKORN-SCHMIDT HARALD F</creatorcontrib><creatorcontrib>BUCHANAN DOUGLAS A</creatorcontrib><creatorcontrib>BALLANTINE ARNE W</creatorcontrib><creatorcontrib>CARTIER EDUARD A</creatorcontrib><creatorcontrib>COOLBAUGH DOUGLAS D</creatorcontrib><creatorcontrib>GOUSEV EVGENI P</creatorcontrib><title>FEOL CAPACITOR AND ITS MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor. SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB2c_X3UXB2DHB09gzxD1Jw9HNR8AwJVvB19At1c3QOCQ3y9HNX8HUN8fB34WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGxgamhqYmlo7GRCkCAKo1JTQ</recordid><startdate>20030221</startdate><enddate>20030221</enddate><creator>OKORN-SCHMIDT HARALD F</creator><creator>BUCHANAN DOUGLAS A</creator><creator>BALLANTINE ARNE W</creator><creator>CARTIER EDUARD A</creator><creator>COOLBAUGH DOUGLAS D</creator><creator>GOUSEV EVGENI P</creator><scope>EVB</scope></search><sort><creationdate>20030221</creationdate><title>FEOL CAPACITOR AND ITS MANUFACTURING METHOD</title><author>OKORN-SCHMIDT HARALD F ; BUCHANAN DOUGLAS A ; BALLANTINE ARNE W ; CARTIER EDUARD A ; COOLBAUGH DOUGLAS D ; GOUSEV EVGENI P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2003051549A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OKORN-SCHMIDT HARALD F</creatorcontrib><creatorcontrib>BUCHANAN DOUGLAS A</creatorcontrib><creatorcontrib>BALLANTINE ARNE W</creatorcontrib><creatorcontrib>CARTIER EDUARD A</creatorcontrib><creatorcontrib>COOLBAUGH DOUGLAS D</creatorcontrib><creatorcontrib>GOUSEV EVGENI P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OKORN-SCHMIDT HARALD F</au><au>BUCHANAN DOUGLAS A</au><au>BALLANTINE ARNE W</au><au>CARTIER EDUARD A</au><au>COOLBAUGH DOUGLAS D</au><au>GOUSEV EVGENI P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FEOL CAPACITOR AND ITS MANUFACTURING METHOD</title><date>2003-02-21</date><risdate>2003</risdate><abstract>PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor. SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2003051549A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title FEOL CAPACITOR AND ITS MANUFACTURING METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T18%3A17%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OKORN-SCHMIDT%20HARALD%20F&rft.date=2003-02-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2003051549A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true