SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To prevent malfunction of a circuit caused by a difference of a parasite capacity by equalizing the parasite capacity of a data line comprising a plurality of wiring layers. SOLUTION: A first area and a second area transmit data having simultaneous transmission by using the dat...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: NAKAMURA TOSHIKAZU, MISHIRO TOSHIYA
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To prevent malfunction of a circuit caused by a difference of a parasite capacity by equalizing the parasite capacity of a data line comprising a plurality of wiring layers. SOLUTION: A first area and a second area transmit data having simultaneous transmission by using the data line different in their wiring layers. An upper and lower relation of the data line is reverse in the first and second areas. A switching area replaces the data line of the first area and the data line of the second area with each other. Since the parasite capacity adhered to both the data lines is substantially equal, a delay time of a signal transmitted to the data line is equal, and the malfunction of the circuit caused by the difference of the parasite capacity can be prevented. In a semiconductor integrated circuit alternately arranging a memory cell array and a sense amplification row, the first and second areas are formed on a memory cell array, and replacement of the data lines in the switching area can be facilitated by forming the switching area on the sense amplification row.