SYNCHRONOUS COUNTER

PROBLEM TO BE SOLVED: To provide a synchronous counter that can enable high-speed processing of a multi-bit counter. SOLUTION: The synchronous counter is provided with first to n-th count circuits, first to n-th decoding means, first to (n-1)-th timing adjustment means and (n-i) (i=2, 3,..., n-1) stages of first to (n-2)-th shifting means. A first carry signal, being an output of the first timing adjustment means, is fed to the 1st shifting means, an output of the first shifting means is fed to the second count circuit, the output of the first timing adjustment means is fed to the second decoding means; similarly an i-th carry signal being an output of an i-th timing adjustment means is fed to an i-th shifting means, an output of the i-th shifting means is fed to an (i+1)-th count circuit, and an output of the i-th timing adjustment means is fed to the (i+1)-th decoding means to set a decode value of the i-th decoding means to be 2 .