BIAS CIRCUIT

PROBLEM TO BE SOLVED: To suppress intermodulated components. SOLUTION: The bias circuit of FETs (or bipolar transistors) Q1 and Q2 comprises: a notch filter composed of two inductors of an inductance L and a one-terminal grounded capacitor of capacitance 2C; and a one-side power feeding circuit from...

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Hauptverfasser:	ITO AKIRA, YAMASHITA TESSHIN, OGUCHI NOBUTAKA
Format:	Patent
Sprache:	eng
Schlagworte:	AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRICITY RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE WAVEGUIDES
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creator	ITO AKIRA YAMASHITA TESSHIN OGUCHI NOBUTAKA
description	PROBLEM TO BE SOLVED: To suppress intermodulated components. SOLUTION: The bias circuit of FETs (or bipolar transistors) Q1 and Q2 comprises: a notch filter composed of two inductors of an inductance L and a one-terminal grounded capacitor of capacitance 2C; and a one-side power feeding circuit from a bias power supply VG, etc. The blocking frequency of the notch filter is set at a difference frequency Δf of an input signal component.
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SOLUTION: The bias circuit of FETs (or bipolar transistors) Q1 and Q2 comprises: a notch filter composed of two inductors of an inductance L and a one-terminal grounded capacitor of capacitance 2C; and a one-side power feeding circuit from a bias power supply VG, etc. The blocking frequency of the notch filter is set at a difference frequency Δf of an input signal component.</description><edition>7</edition><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE ; WAVEGUIDES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021025&DB=EPODOC&CC=JP&NR=2002314347A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021025&DB=EPODOC&CC=JP&NR=2002314347A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ITO AKIRA</creatorcontrib><creatorcontrib>YAMASHITA TESSHIN</creatorcontrib><creatorcontrib>OGUCHI NOBUTAKA</creatorcontrib><title>BIAS CIRCUIT</title><description>PROBLEM TO BE SOLVED: To suppress intermodulated components. SOLUTION: The bias circuit of FETs (or bipolar transistors) Q1 and Q2 comprises: a notch filter composed of two inductors of an inductance L and a one-terminal grounded capacitor of capacitance 2C; and a one-side power feeding circuit from a bias power supply VG, etc. The blocking frequency of the notch filter is set at a difference frequency Δf of an input signal component.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</subject><subject>WAVEGUIDES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOBx8nQMVnD2DHIO9QzhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZGxoYmxibmjsZEKQIAu1UcrQ</recordid><startdate>20021025</startdate><enddate>20021025</enddate><creator>ITO AKIRA</creator><creator>YAMASHITA TESSHIN</creator><creator>OGUCHI NOBUTAKA</creator><scope>EVB</scope></search><sort><creationdate>20021025</creationdate><title>BIAS CIRCUIT</title><author>ITO AKIRA ; YAMASHITA TESSHIN ; OGUCHI NOBUTAKA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002314347A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</topic><topic>WAVEGUIDES</topic><toplevel>online_resources</toplevel><creatorcontrib>ITO AKIRA</creatorcontrib><creatorcontrib>YAMASHITA TESSHIN</creatorcontrib><creatorcontrib>OGUCHI NOBUTAKA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ITO AKIRA</au><au>YAMASHITA TESSHIN</au><au>OGUCHI NOBUTAKA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BIAS CIRCUIT</title><date>2002-10-25</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To suppress intermodulated components. SOLUTION: The bias circuit of FETs (or bipolar transistors) Q1 and Q2 comprises: a notch filter composed of two inductors of an inductance L and a one-terminal grounded capacitor of capacitance 2C; and a one-side power feeding circuit from a bias power supply VG, etc. The blocking frequency of the notch filter is set at a difference frequency Δf of an input signal component.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects	AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRICITY RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE WAVEGUIDES
title	BIAS CIRCUIT
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