THREE-DIMENSIONAL MULTICHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a three-dimensional multichip package containing a chip selection pad formed at a chip level. SOLUTION: The three-dimensional multichip package 100 is constituted by laminating four semiconductor integrated-circuit elements 110, 120, 130, 140. The elements 110, 120,...

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Bibliographische Detailangaben
Hauptverfasser: KYO SHIIN, TEI MEIKI, KANG IN-KU, LEE KWAN-JAI, KIM KYOSHO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a three-dimensional multichip package containing a chip selection pad formed at a chip level. SOLUTION: The three-dimensional multichip package 100 is constituted by laminating four semiconductor integrated-circuit elements 110, 120, 130, 140. The elements 110, 120, 130, 140 comprise integrated-circuit chips, one chip selection terminal 12a, three pieces of chip selection pads 12c, an insulating layer, three pieces of first metal interconnections 15, many pieces of upper connecting terminals 22, 22a, many pieces of lower connecting terminals 23, 23a, 23c and many pieces of trench interconnections 14. The terminal 12a formed in the elements 110, 120, 130, 140 is separated automatically, via the three pieces of pads 12c formed at the chip level.