CLOCK SIGNAL CORRECTING CIRCUIT AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To correct the duty ratio of clock signals with accuracy by means of a simple circuit. SOLUTION: A frequency dividing means 20 generates a frequency-divided clock signal by dividing the frequency of an input clock signal into 1/n frequencies (n: a natural number). An edge detecting means 21 detects the edge of the frequency-divided clock signal. A delaying means 22 generates a delayed frequency-divided clock signal by delaying the frequency-divided clock signal in accordance with the detected results of the detecting means 21. An arithmetic means 23 generates an output clock signal by operating the frequency-divided clock signal and delayed frequency-divided clock signal.