PREPARATION METHOD OF IMPEDANCE NET MODEL

PROBLEM TO BE SOLVED: To provide a preparation method of impedance net models for reducing the scale of an inverse matrix operation for converting a multi-port F matrix to an admittance matrix, for taking out one portion of the structure of a semiconductor substrate, for reutilizing calculated resul...

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1. Verfasser: AOYAMA SHINTARO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a preparation method of impedance net models for reducing the scale of an inverse matrix operation for converting a multi-port F matrix to an admittance matrix, for taking out one portion of the structure of a semiconductor substrate, for reutilizing calculated results, and for adjusting a resolution according to the degree of density in the structure formed on the semiconductor substrate when a lattice-like impedance net model of the semiconductor substrate is degenerated by utilizing the multi-port F matrix. SOLUTION: This preparation method includes a first step S1 for dividing the semiconductor substrate into a plurality of regions, a second step S2 for generating a second impedance net model for a specified, arbitrary region, and a third step S3 for connecting the second impedance net model obtained for the entire region by a specific second connection impedance element, and for generating an optimum impedance net model.