PROGRAMMABLE CELL ARRAY CIRCUIT
PROBLEM TO BE SOLVED: To provide a programmable cell array circuit in which an oscillation action is prevented when power is supplied and while writing is conducted to a memory cell, an LSI can be normally operated without making excessive current flow to the LSI, and optional data can be simultaneo...
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creator | NAKADA HIROSHI KONISHI RYUSUKE ITO HIDEYUKI |
description | PROBLEM TO BE SOLVED: To provide a programmable cell array circuit in which an oscillation action is prevented when power is supplied and while writing is conducted to a memory cell, an LSI can be normally operated without making excessive current flow to the LSI, and optional data can be simultaneously stored in each LUT as an SRAM. SOLUTION: This programmable cell array circuit is constructed by arranging a plurality of programmable cells, and adjacent cell connection control circuits 2A and B for connecting/disconnecting a connection line are provided between the adjacent programmable cells IA and B. A memory control circuit 3 for controlling the adjacent programmable cells are also provided to output an adjacent cell connection control signal, an instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuits while data are written to a LUT, an instruction signal for connecting the connection line is outputted to the adjacent cell connection control circuits when the writing the data is finished, the instruction signal for disconnecting the connection line is always outputted to the adjacent cell connection control circuits when used as an SRAM, and the instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuit when the power is supplied. |
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SOLUTION: This programmable cell array circuit is constructed by arranging a plurality of programmable cells, and adjacent cell connection control circuits 2A and B for connecting/disconnecting a connection line are provided between the adjacent programmable cells IA and B. A memory control circuit 3 for controlling the adjacent programmable cells are also provided to output an adjacent cell connection control signal, an instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuits while data are written to a LUT, an instruction signal for connecting the connection line is outputted to the adjacent cell connection control circuits when the writing the data is finished, the instruction signal for disconnecting the connection line is always outputted to the adjacent cell connection control circuits when used as an SRAM, and the instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuit when the power is supplied.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020607&DB=EPODOC&CC=JP&NR=2002164780A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020607&DB=EPODOC&CC=JP&NR=2002164780A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAKADA HIROSHI</creatorcontrib><creatorcontrib>KONISHI RYUSUKE</creatorcontrib><creatorcontrib>ITO HIDEYUKI</creatorcontrib><title>PROGRAMMABLE CELL ARRAY CIRCUIT</title><description>PROBLEM TO BE SOLVED: To provide a programmable cell array circuit in which an oscillation action is prevented when power is supplied and while writing is conducted to a memory cell, an LSI can be normally operated without making excessive current flow to the LSI, and optional data can be simultaneously stored in each LUT as an SRAM. SOLUTION: This programmable cell array circuit is constructed by arranging a plurality of programmable cells, and adjacent cell connection control circuits 2A and B for connecting/disconnecting a connection line are provided between the adjacent programmable cells IA and B. A memory control circuit 3 for controlling the adjacent programmable cells are also provided to output an adjacent cell connection control signal, an instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuits while data are written to a LUT, an instruction signal for connecting the connection line is outputted to the adjacent cell connection control circuits when the writing the data is finished, the instruction signal for disconnecting the connection line is always outputted to the adjacent cell connection control circuits when used as an SRAM, and the instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuit when the power is supplied.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAPCPJ3D3L09XV08nFVcHb18VFwDApyjFRw9gxyDvUM4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGRoZmJuYWBo7GRCkCABF8IgE</recordid><startdate>20020607</startdate><enddate>20020607</enddate><creator>NAKADA HIROSHI</creator><creator>KONISHI RYUSUKE</creator><creator>ITO HIDEYUKI</creator><scope>EVB</scope></search><sort><creationdate>20020607</creationdate><title>PROGRAMMABLE CELL ARRAY CIRCUIT</title><author>NAKADA HIROSHI ; KONISHI RYUSUKE ; ITO HIDEYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002164780A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>NAKADA HIROSHI</creatorcontrib><creatorcontrib>KONISHI RYUSUKE</creatorcontrib><creatorcontrib>ITO HIDEYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAKADA HIROSHI</au><au>KONISHI RYUSUKE</au><au>ITO HIDEYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROGRAMMABLE CELL ARRAY CIRCUIT</title><date>2002-06-07</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To provide a programmable cell array circuit in which an oscillation action is prevented when power is supplied and while writing is conducted to a memory cell, an LSI can be normally operated without making excessive current flow to the LSI, and optional data can be simultaneously stored in each LUT as an SRAM. SOLUTION: This programmable cell array circuit is constructed by arranging a plurality of programmable cells, and adjacent cell connection control circuits 2A and B for connecting/disconnecting a connection line are provided between the adjacent programmable cells IA and B. A memory control circuit 3 for controlling the adjacent programmable cells are also provided to output an adjacent cell connection control signal, an instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuits while data are written to a LUT, an instruction signal for connecting the connection line is outputted to the adjacent cell connection control circuits when the writing the data is finished, the instruction signal for disconnecting the connection line is always outputted to the adjacent cell connection control circuits when used as an SRAM, and the instruction signal for disconnecting the connection line is outputted to the adjacent cell connection control circuit when the power is supplied.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | PROGRAMMABLE CELL ARRAY CIRCUIT |
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