METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM

PROBLEM TO BE SOLVED: To provide a method for preventing micro cracks of an inter level dielectric caused from a stress applied to a bonding pad when bonding in a process of semiconductor. SOLUTION: The inner level dielectric IL3 between metal layers Mn, Mn-1 is strengthened by a conductive via patt...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: RINCON REYNALDO, SUNDARARAMAN VISWANATHAN, HOTCHKISS GREGORY B, EDWARDS DARVIN R, CHISHOLM MICHAEL F
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator RINCON REYNALDO
SUNDARARAMAN VISWANATHAN
HOTCHKISS GREGORY B
EDWARDS DARVIN R
CHISHOLM MICHAEL F
description PROBLEM TO BE SOLVED: To provide a method for preventing micro cracks of an inter level dielectric caused from a stress applied to a bonding pad when bonding in a process of semiconductor. SOLUTION: The inner level dielectric IL3 between metal layers Mn, Mn-1 is strengthened by a conductive via pattern 110 between the metal interconnecting layer Mn in a region of the bonding pad and the lower metal interconnecting layer Mn-1. The conductive via layer 110 includes, for example, a grid of a parallel rail or a cross hatch rail. The conductive via layer 110 prevents the micro crack caused from the stress applied to the bonding pad 112 by dispersing the stress concentration laterally.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2002134509A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2002134509A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2002134509A3</originalsourceid><addsrcrecordid>eNqNi7EKwjAUALM4iPoPD3chtjo4hueLibwkJU0Fp1IkTqKF-v8YwQ9wOg7u5qJ3lEw4gg4R2hQ7TF1UzFewHiOp1voTOEKjvEXF0FAspVMeCYKG1rLF4IHpQlyWRLGoJ0zfT1t2SzG7D48pr35ciLWmhGaTx1efp3G45Wd-9-emkrLa1ru9PKj6r-gD44sz3g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM</title><source>esp@cenet</source><creator>RINCON REYNALDO ; SUNDARARAMAN VISWANATHAN ; HOTCHKISS GREGORY B ; EDWARDS DARVIN R ; CHISHOLM MICHAEL F</creator><creatorcontrib>RINCON REYNALDO ; SUNDARARAMAN VISWANATHAN ; HOTCHKISS GREGORY B ; EDWARDS DARVIN R ; CHISHOLM MICHAEL F</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a method for preventing micro cracks of an inter level dielectric caused from a stress applied to a bonding pad when bonding in a process of semiconductor. SOLUTION: The inner level dielectric IL3 between metal layers Mn, Mn-1 is strengthened by a conductive via pattern 110 between the metal interconnecting layer Mn in a region of the bonding pad and the lower metal interconnecting layer Mn-1. The conductive via layer 110 includes, for example, a grid of a parallel rail or a cross hatch rail. The conductive via layer 110 prevents the micro crack caused from the stress applied to the bonding pad 112 by dispersing the stress concentration laterally.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020510&amp;DB=EPODOC&amp;CC=JP&amp;NR=2002134509A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020510&amp;DB=EPODOC&amp;CC=JP&amp;NR=2002134509A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RINCON REYNALDO</creatorcontrib><creatorcontrib>SUNDARARAMAN VISWANATHAN</creatorcontrib><creatorcontrib>HOTCHKISS GREGORY B</creatorcontrib><creatorcontrib>EDWARDS DARVIN R</creatorcontrib><creatorcontrib>CHISHOLM MICHAEL F</creatorcontrib><title>METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM</title><description>PROBLEM TO BE SOLVED: To provide a method for preventing micro cracks of an inter level dielectric caused from a stress applied to a bonding pad when bonding in a process of semiconductor. SOLUTION: The inner level dielectric IL3 between metal layers Mn, Mn-1 is strengthened by a conductive via pattern 110 between the metal interconnecting layer Mn in a region of the bonding pad and the lower metal interconnecting layer Mn-1. The conductive via layer 110 includes, for example, a grid of a parallel rail or a cross hatch rail. The conductive via layer 110 prevents the micro crack caused from the stress applied to the bonding pad 112 by dispersing the stress concentration laterally.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwjAUALM4iPoPD3chtjo4hueLibwkJU0Fp1IkTqKF-v8YwQ9wOg7u5qJ3lEw4gg4R2hQ7TF1UzFewHiOp1voTOEKjvEXF0FAspVMeCYKG1rLF4IHpQlyWRLGoJ0zfT1t2SzG7D48pr35ciLWmhGaTx1efp3G45Wd-9-emkrLa1ru9PKj6r-gD44sz3g</recordid><startdate>20020510</startdate><enddate>20020510</enddate><creator>RINCON REYNALDO</creator><creator>SUNDARARAMAN VISWANATHAN</creator><creator>HOTCHKISS GREGORY B</creator><creator>EDWARDS DARVIN R</creator><creator>CHISHOLM MICHAEL F</creator><scope>EVB</scope></search><sort><creationdate>20020510</creationdate><title>METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM</title><author>RINCON REYNALDO ; SUNDARARAMAN VISWANATHAN ; HOTCHKISS GREGORY B ; EDWARDS DARVIN R ; CHISHOLM MICHAEL F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002134509A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>RINCON REYNALDO</creatorcontrib><creatorcontrib>SUNDARARAMAN VISWANATHAN</creatorcontrib><creatorcontrib>HOTCHKISS GREGORY B</creatorcontrib><creatorcontrib>EDWARDS DARVIN R</creatorcontrib><creatorcontrib>CHISHOLM MICHAEL F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RINCON REYNALDO</au><au>SUNDARARAMAN VISWANATHAN</au><au>HOTCHKISS GREGORY B</au><au>EDWARDS DARVIN R</au><au>CHISHOLM MICHAEL F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM</title><date>2002-05-10</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To provide a method for preventing micro cracks of an inter level dielectric caused from a stress applied to a bonding pad when bonding in a process of semiconductor. SOLUTION: The inner level dielectric IL3 between metal layers Mn, Mn-1 is strengthened by a conductive via pattern 110 between the metal interconnecting layer Mn in a region of the bonding pad and the lower metal interconnecting layer Mn-1. The conductive via layer 110 includes, for example, a grid of a parallel rail or a cross hatch rail. The conductive via layer 110 prevents the micro crack caused from the stress applied to the bonding pad 112 by dispersing the stress concentration laterally.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2002134509A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
LAYERED PRODUCTS
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
TRANSPORTING
title METHOD FOR STRUCTURALLY INCREASING MECHANICAL PERFORMANCE OF SILICON LEVEL INTERCONNECTING FILM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T12%3A55%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RINCON%20REYNALDO&rft.date=2002-05-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2002134509A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true