CACHE CONTROL METHOD AND CACHE CONTROL SYSTEM

PROBLEM TO BE SOLVED: To directly select the optional number of caches to be actually used from the plural caches by a main memory access instruction. SOLUTION: To the main memory access instructions such as a loading instruction executed in a processor core 1, cache selection flags F1-F4 in one- to...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	NAGANO TOMOAKI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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