CACHE CONTROL METHOD AND CACHE CONTROL SYSTEM

PROBLEM TO BE SOLVED: To directly select the optional number of caches to be actually used from the plural caches by a main memory access instruction. SOLUTION: To the main memory access instructions such as a loading instruction executed in a processor core 1, cache selection flags F1-F4 in one- to-one correspondence with the caches 71-74 are added. At the time of executing the main memory access instructions, the cache selection flags F1-F4 are sent out to the respective caches 71-74. In the case of the loading instruction, the respective caches 71-74 judge a hit and an error based on a main memory address sent out from the processor core 1 and output judged results. AND circuits 706-709 AND the judged results and the cache selection flags F1-F4 and obtain a true hit judged result. In the case of the hit, cache data from the hit cache are selected in a selector 705 and returned to the processor core 1.