CIRCUIT PACKAGE
PROBLEM TO BE SOLVED: To provide a circuit package which has a package module with a small build. SOLUTION: This circuit package comprises a conductor belt as a base 211, a master chip 22, and a slave chip 23; and the master chip 22 is stuck on the base 211 on a flat packaging basis, the slave chip...
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| creator | CHENG CHUANG YUNG WEN CHIANG HUA JUI CHANG HSUAN NING HUANG CHANG TU FENG HSIEN WEN-LO CHIEH HU CHIA YU HUANG FU PIN CHEN HUI MING CHANG CHUANG |
| description | PROBLEM TO BE SOLVED: To provide a circuit package which has a package module with a small build. SOLUTION: This circuit package comprises a conductor belt as a base 211, a master chip 22, and a slave chip 23; and the master chip 22 is stuck on the base 211 on a flat packaging basis, the slave chip 23 having a projection is stuck on the master chip 22 and base 211 on a flip-chip basis at the same time, and the master chip 22 and slave chip 23 are put one over the other. The height of the package composed of the master chip 22 and slave chip 23 is less than the overall thickness of a three-layered substrate. |
| format | Patent |
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The height of the package composed of the master chip 22 and slave chip 23 is less than the overall thickness of a three-layered substrate.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020412&DB=EPODOC&CC=JP&NR=2002110894A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020412&DB=EPODOC&CC=JP&NR=2002110894A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHENG CHUANG YUNG</creatorcontrib><creatorcontrib>WEN CHIANG HUA</creatorcontrib><creatorcontrib>JUI CHANG HSUAN</creatorcontrib><creatorcontrib>NING HUANG</creatorcontrib><creatorcontrib>CHANG TU FENG</creatorcontrib><creatorcontrib>HSIEN WEN-LO</creatorcontrib><creatorcontrib>CHIEH HU CHIA</creatorcontrib><creatorcontrib>YU HUANG FU</creatorcontrib><creatorcontrib>PIN CHEN HUI</creatorcontrib><creatorcontrib>MING CHANG CHUANG</creatorcontrib><title>CIRCUIT PACKAGE</title><description>PROBLEM TO BE SOLVED: To provide a circuit package which has a package module with a small build. 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The height of the package composed of the master chip 22 and slave chip 23 is less than the overall thickness of a three-layered substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOB39gxyDvUMUQhwdPZ2dHflYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZGhoYGFpYmjsZEKQIAEcIdfw</recordid><startdate>20020412</startdate><enddate>20020412</enddate><creator>CHENG CHUANG YUNG</creator><creator>WEN CHIANG HUA</creator><creator>JUI CHANG HSUAN</creator><creator>NING HUANG</creator><creator>CHANG TU FENG</creator><creator>HSIEN WEN-LO</creator><creator>CHIEH HU CHIA</creator><creator>YU HUANG FU</creator><creator>PIN CHEN HUI</creator><creator>MING CHANG CHUANG</creator><scope>EVB</scope></search><sort><creationdate>20020412</creationdate><title>CIRCUIT PACKAGE</title><author>CHENG CHUANG YUNG ; WEN CHIANG HUA ; JUI CHANG HSUAN ; NING HUANG ; CHANG TU FENG ; HSIEN WEN-LO ; CHIEH HU CHIA ; YU HUANG FU ; PIN CHEN HUI ; MING CHANG CHUANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002110894A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHENG CHUANG YUNG</creatorcontrib><creatorcontrib>WEN CHIANG HUA</creatorcontrib><creatorcontrib>JUI CHANG HSUAN</creatorcontrib><creatorcontrib>NING HUANG</creatorcontrib><creatorcontrib>CHANG TU FENG</creatorcontrib><creatorcontrib>HSIEN WEN-LO</creatorcontrib><creatorcontrib>CHIEH HU CHIA</creatorcontrib><creatorcontrib>YU HUANG FU</creatorcontrib><creatorcontrib>PIN CHEN HUI</creatorcontrib><creatorcontrib>MING CHANG CHUANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHENG CHUANG YUNG</au><au>WEN CHIANG HUA</au><au>JUI CHANG HSUAN</au><au>NING HUANG</au><au>CHANG TU FENG</au><au>HSIEN WEN-LO</au><au>CHIEH HU CHIA</au><au>YU HUANG FU</au><au>PIN CHEN HUI</au><au>MING CHANG CHUANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CIRCUIT PACKAGE</title><date>2002-04-12</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To provide a circuit package which has a package module with a small build. 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| language | eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | CIRCUIT PACKAGE |
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