MULTI-PORT MEMORY DEVICE

PROBLEM TO BE SOLVED: To ensure a large number of ports without including any complicate arbitrating means in a simple constitution. SOLUTION: An access timing and access order to a DRAM 4 for each system within one cycle of a sequence operation are fixed, and serial/parallel converting circuits 1a and 1b perform serial/parallel conversion synchronously with a writing request timing, and write buffers 2a and 2b temporarily store the output signals of the serial/parallel converting circuits 1a and 1b synchronously with a sequence, and read buffers 5a and 5b temporarily store data read from the DRAM 4 synchronously with the sequence, and parallel/serial converting circuits 6a and 6b convert the parallel data into serial data, and delay adjusting circuits 7a and 7b delays data so that the timing can be matched with the reading request timing.