DIGITAL DELAY CIRCUIT

PROBLEM TO BE SOLVED: To provide a digital delay circuit that can enhance the delay resolution without employing a high-speed clock signal. SOLUTION: A latch 20 latches data RDATA read from a dual port RAM 10 and further a latch 22 latches the data RDATA. The latch 20 executes latching in timing of...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	IIDA HIROSHI, MICHIJIMA FUTOSHI, WATANABE OSAMU, TERADA KENJI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a digital delay circuit that can enhance the delay resolution without employing a high-speed clock signal. SOLUTION: A latch 20 latches data RDATA read from a dual port RAM 10 and further a latch 22 latches the data RDATA. The latch 20 executes latching in timing of a reference clock CLK and the latch 20 executes latching in timing of a delayed clock CLKD. A very-small-delay element 24 delays the reference clock CLK to produce the delay clock CLKD.