WAFER-LEVEL CHIP SIZE PACKAGE AND FORMATION MATERIAL FOR SEALING FOR THE SAME

PROBLEM TO BE SOLVED: To provide a formation material for sealing a wafer-level chip size package that can obtain a package, having small amount for warpage and reliable solder-resistant reflow, heat-resistant shock, and humidity-resistant properties or the like, even if the formation material is ap...

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Bibliographische Detailangaben
Hauptverfasser:	TSUCHIDA SATORU, KOSAKA MASAHIKO, OGATA MASAJI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CHEMISTRY COMPOSITIONS BASED THEREON COMPOSITIONS OF MACROMOLECULAR COMPOUNDS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONSONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS METALLURGY ORGANIC MACROMOLECULAR COMPOUNDS SEMICONDUCTOR DEVICES THEIR PREPARATION OR CHEMICAL WORKING-UP USE OF INORGANIC OR NON-MACROMOLECULAR ORGANIC SUBSTANCES ASCOMPOUNDING INGREDIENTS
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a formation material for sealing a wafer-level chip size package that can obtain a package, having small amount for warpage and reliable solder-resistant reflow, heat-resistant shock, and humidity-resistant properties or the like, even if the formation material is applied to the water- level chip size package, and the wafer-level chip size package that is sealed by the sealing formation material. SOLUTION: In this formation material for sealing for the water-level chip size package, the elastic modulus of a molding is set equal to 1,000 MPa or lower at 25 deg.C, and at the same time, the average thermal coefficient of expansion is 150×10-6/ deg.C or lower at -55 to 150 deg.C. The wafer level chip size package is sealed by the formation material for sealing.