METHOD OF CREATING LAYOUT INFORMATION AND METHOD OF DESIGNING SEMICONDUCTOR SUBSTRATE

PROBLEM TO BE SOLVED: To shorten the wire length and reduce a through hole region for switching over from one wire to another by making possible the insertion of macros having different functions from those of a soft macro or hard macros, into vacant regions of the soft macro consisting of the hard...

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Bibliographische Detailangaben
1. Verfasser: OYAMA JUNICHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To shorten the wire length and reduce a through hole region for switching over from one wire to another by making possible the insertion of macros having different functions from those of a soft macro or hard macros, into vacant regions of the soft macro consisting of the hard macros and standard function elements, to reduce the area of a semiconductor substrate, and to increase the operation speed. SOLUTION: A provisional LEF 120 wherein the outline shape of a macro 100 is defined and a detailed LEF 130 wherein the real shape of the macro 100 is defined are prepared. First, the provisional LEF 120 is used when arranging and wiring the information on logic connections on the semiconductor substrate, and thereafter the provisional LEF 120 is replaced with the detailed LEF 130. Since the SITE of the semiconductor substrate is left over in the region where the macro 100 has been disposed, a repeater can recognize a vacant region 109, and then can insert a circuit for shaping a waveform into that region, thus preventing wires from bypassing the macro 100.