IC TESTER AND ITS CONTROL METHOD
PROBLEM TO BE SOLVED: To provide an IC tester capable of efficiently testing an IC even in the case that one station becomes test initiation waiting state and two stations do not become test state simultaneously in an IC tester functioning in a multi-station mode. SOLUTION: A program execution devic...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide an IC tester capable of efficiently testing an IC even in the case that one station becomes test initiation waiting state and two stations do not become test state simultaneously in an IC tester functioning in a multi-station mode. SOLUTION: A program execution device 3 counts down retest effective time set by a setting device 1 upon IC test execution. In the case that a certain station 6a becomes a test initiation waiting state, a retest judging device 5 confirms that the count down retest effective time is not yet 0 and then outputs a signal for interrupting the executing IC test. The program execution device 3 input with the interruption signal makes all stations 6a and 6b simultaneously execute the IC test again. |
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