METHOD OF MANUFACTURING INSULATED GATE SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve a problem in the conventional case wherein micronization of trench formation is indispensable when the cell density of a power MOSFET is improved, working dimension of a trench opening is limited to an optical limit of an aligner, and introduction of new installation is necessary for micromachining. SOLUTION: A mask is formed on a CVD oxide film 5 except a part turning to the trench aperture part 6, etching is performed and the trench aperture 6 is formed. A second CVD oxide film is formed, and a slide wall film 8 is formed by using anisotropic RIE of the second CVD oxide film. A channel layer 4 is penetrated by dry etching using the CVD oxide film 5 and the side wall film 8 as masks. A fine pattern which is about one-half the conventional case can be formed without introducing new installation by the formation of a trench reaching a drain region 2, and the cell density of a power MOSFET can be improved up to 2 times.