ACTIVE MATRIX SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide an active matrix substrate with a high yield and excellent characteristics by four photolithography operations. SOLUTION: In a first process, a scanning line 11 and a gate electrode 12 extending from the scanning line are formed on a glass substrate 1. In a second pr...

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Hauptverfasser:	SHIMODOUSONO HISASHI, HAYASE TAKASUKE, TANAKA HIROAKI, TAKECHI KAZUE, HARANO TOSHIHIKO, ITOIDA SATOSHI, KUROBA SHOICHI, IHARA HIROSHI, UCHIDA HIROYUKI, DOI SATOSHI, KIDO SHUSAKU, NAKADA SHINICHI, YOSHIKAWA TAE, KIMURA SHIGERU, HAMADA TSUTOMU, MAEDA AKIYOSHI, WATANABE TAKAHIKO
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING BASIC ELECTRIC ELEMENTS CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY DISPLAYING EDUCATION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FREQUENCY-CHANGING LABELS OR NAME-PLATES NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS SEALS SEMICONDUCTOR DEVICES SIGNS TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
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Zusammenfassung:	PROBLEM TO BE SOLVED: To provide an active matrix substrate with a high yield and excellent characteristics by four photolithography operations. SOLUTION: In a first process, a scanning line 11 and a gate electrode 12 extending from the scanning line are formed on a glass substrate 1. In a second process, a gate insulating layer 2 and a semiconductor layer 20 consisting of an amorphous silicon layer 21 and an amorphous silicon layer 22 are laminated to form a semiconductor layer 20 of a TFT portion Tf. In a third process, a transparent conductive layer 40 and a metal layer 30 are laminated to form a signal line 31, a drain electrode 32 extending from the signal line, a pixel electrode 41 and a source electrode 33 extending from the pixel electrode. Then, an n+ amorphous silicon layer 22 in a channel gap 23 is etched and removed. In a fourth process, a protection insulating layer 3 is formed and the protection insulating layer 3 on the pixel electrode 41 and the metal layer 30 are etched and removed.