LATCH-CONTROLLABLE INSULATION GATE BIPOLAR TRANSISTOR

PROBLEM TO BE SOLVED: To provide an insulation gate bipolar transistor that can be latch- controlled while being used for high power. SOLUTION: The insulation gate bipolar transistor is provided with a first semiconductor region (P-type well) 56 with a first conduction type (P type) and first and second surfaces, a second semiconductor region (N-type well) 58 that is located at the first surface side of the region and has a second conduction type (N type), an N-type third semiconductor region that is located at the second surface side of the first semiconductor region, a P-type fourth semiconductor region (P-type base) 60 being formed on the third semiconductor region, an N-type fifth semiconductor region 62 being formed on the fourth region, a P-type sixth semiconductor region being formed on the fifth region, further a first plane gate 64 for forming a first field effect transistor along with the first, third, and fourth semiconductor regions, a second trench gate 68 for forming a second FET along with the fourth - sixth semiconductor regions being formed in a groove, a first electrode region 72 in contact with the third, fifth, and sixth semiconductor regions, and a second electrode 74 in contact with the second semiconductor region 58.