METHOD FOR ARRANGING ELECTRONIC COMPONENT AND COMPUTER-READABLE RECORDING MEDIUM WITH ARRANGEMENT PROGRAM OF ELECTRONIC COMPONENT RECORDED THEREON

PROBLEM TO BE SOLVED: To provide a method by which delay due to wiring is father reduced, so as to meet the need of quickening a processor by solving the problem where the delay due to wiring cannot be made minimum, when an arrangement method for minimizing the wiring length is employed in the case of arranging a gate on a chip. SOLUTION: When arranging a gate on a chip, a delay estimated value per gate stage is calculated from a target machine cycle and the number of the logic gate stages from a start point flip flop to an end flip flop(path), and the limited value of the wiring length of a net in each stage is calculated from the delay estimated value and the delay characteristics of the gate of each stage, and the limited value is used as the target function of the arrangement.