MICROCOMPUTER/FLOATING POINT PROCESSING INTERFACE AND ITS METHOD

PROBLEM TO BE SOLVED: To improve performance such as processing capability by closely synchronizing both arithmetic operations. SOLUTION: In a computer system having a CPU execution pipe line 160 equipped with a central processing unit (CPU) decoder pipe stage and an FPU execution pipe line 162 equipped with a floating point unit (FPU) decoder pipe stage, a first instruction is transmitted to a CPU decoder pipe stage (a), the first instruction is transmitted to an FPU decoder pipe stage (b), a signal indicating that the first instruction is accepted by the CPU decoder pipe stage is generated (c), a signal indicating that the first instruction is accepted by an FPU decoder pipe stage is generated (d), a second instruction is transmitted to a CPU decoder pipe stage in response to the step d (e), and the second instruction is transmitted to an FPU decoder pipe stage in response to the step c. Corresponding devices are also provided.