FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR
PROBLEM TO BE SOLVED: To provide a field effect transistor with source/drain region of lift structure, which prevents facets that are produced when the source/drain regions are formed through the selective growth of an epitaxial layer and its manufacturing method. SOLUTION: A gate stack is formed on...
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creator | LEE GIL-GWANG SO GENSHO BOKU SEIU SAI TAIKI |
description | PROBLEM TO BE SOLVED: To provide a field effect transistor with source/drain region of lift structure, which prevents facets that are produced when the source/drain regions are formed through the selective growth of an epitaxial layer and its manufacturing method. SOLUTION: A gate stack is formed on a semiconductor substrate 100 where an element isolation film 102 is formed, and an insulating film used for the formation of a gate spacer 110' is formed over the entire surface of the semiconductor substrate, where the gate stack has been formed. The insulating film is subjected to overetching, to make its surface lower than that of the semiconductor substrate, a gate spacer is formed on the side of the gate stack, then an epitaxial layer is selectively grown on the side and base of the semiconductor substrate which are exposed by overetching, and first source/drain region 112 and second source/drain regions 114 are formed. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2001144290A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2001144290A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2001144290A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQgOEuDqK-w-EutrVLx5DcmUibyOWCk5QicRIt1PdHBB_A6eeDf1lcyWFnAIlQCwgrH12UwHBxYiGGxBr3hpXzEAg6RwJROGlJjKC8gV75ROpr54_Qo9hgQCwyUuB1sbiPjzlvfl0VW0LRdpen15DnabzlZ34Pp3NdllXVNHVbqsNf0wdkrTM2</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR</title><source>esp@cenet</source><creator>LEE GIL-GWANG ; SO GENSHO ; BOKU SEIU ; SAI TAIKI</creator><creatorcontrib>LEE GIL-GWANG ; SO GENSHO ; BOKU SEIU ; SAI TAIKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a field effect transistor with source/drain region of lift structure, which prevents facets that are produced when the source/drain regions are formed through the selective growth of an epitaxial layer and its manufacturing method. SOLUTION: A gate stack is formed on a semiconductor substrate 100 where an element isolation film 102 is formed, and an insulating film used for the formation of a gate spacer 110' is formed over the entire surface of the semiconductor substrate, where the gate stack has been formed. The insulating film is subjected to overetching, to make its surface lower than that of the semiconductor substrate, a gate spacer is formed on the side of the gate stack, then an epitaxial layer is selectively grown on the side and base of the semiconductor substrate which are exposed by overetching, and first source/drain region 112 and second source/drain regions 114 are formed.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010525&DB=EPODOC&CC=JP&NR=2001144290A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010525&DB=EPODOC&CC=JP&NR=2001144290A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE GIL-GWANG</creatorcontrib><creatorcontrib>SO GENSHO</creatorcontrib><creatorcontrib>BOKU SEIU</creatorcontrib><creatorcontrib>SAI TAIKI</creatorcontrib><title>FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR</title><description>PROBLEM TO BE SOLVED: To provide a field effect transistor with source/drain region of lift structure, which prevents facets that are produced when the source/drain regions are formed through the selective growth of an epitaxial layer and its manufacturing method. SOLUTION: A gate stack is formed on a semiconductor substrate 100 where an element isolation film 102 is formed, and an insulating film used for the formation of a gate spacer 110' is formed over the entire surface of the semiconductor substrate, where the gate stack has been formed. The insulating film is subjected to overetching, to make its surface lower than that of the semiconductor substrate, a gate spacer is formed on the side of the gate stack, then an epitaxial layer is selectively grown on the side and base of the semiconductor substrate which are exposed by overetching, and first source/drain region 112 and second source/drain regions 114 are formed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQgOEuDqK-w-EutrVLx5DcmUibyOWCk5QicRIt1PdHBB_A6eeDf1lcyWFnAIlQCwgrH12UwHBxYiGGxBr3hpXzEAg6RwJROGlJjKC8gV75ROpr54_Qo9hgQCwyUuB1sbiPjzlvfl0VW0LRdpen15DnabzlZ34Pp3NdllXVNHVbqsNf0wdkrTM2</recordid><startdate>20010525</startdate><enddate>20010525</enddate><creator>LEE GIL-GWANG</creator><creator>SO GENSHO</creator><creator>BOKU SEIU</creator><creator>SAI TAIKI</creator><scope>EVB</scope></search><sort><creationdate>20010525</creationdate><title>FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR</title><author>LEE GIL-GWANG ; SO GENSHO ; BOKU SEIU ; SAI TAIKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2001144290A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE GIL-GWANG</creatorcontrib><creatorcontrib>SO GENSHO</creatorcontrib><creatorcontrib>BOKU SEIU</creatorcontrib><creatorcontrib>SAI TAIKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE GIL-GWANG</au><au>SO GENSHO</au><au>BOKU SEIU</au><au>SAI TAIKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR</title><date>2001-05-25</date><risdate>2001</risdate><abstract>PROBLEM TO BE SOLVED: To provide a field effect transistor with source/drain region of lift structure, which prevents facets that are produced when the source/drain regions are formed through the selective growth of an epitaxial layer and its manufacturing method. SOLUTION: A gate stack is formed on a semiconductor substrate 100 where an element isolation film 102 is formed, and an insulating film used for the formation of a gate spacer 110' is formed over the entire surface of the semiconductor substrate, where the gate stack has been formed. The insulating film is subjected to overetching, to make its surface lower than that of the semiconductor substrate, a gate spacer is formed on the side of the gate stack, then an epitaxial layer is selectively grown on the side and base of the semiconductor substrate which are exposed by overetching, and first source/drain region 112 and second source/drain regions 114 are formed.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | FIELD EFFECT TRANSISTOR WITH SOURCE/DRAIN OF LIFT STRUCTURE AND MANUFACTURING METHOD THEREFOR |
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