INTEGRATED CIRCUIT COMPRISING DIFFUSION-PREVENTIVE BARRIER LAYER WITH INTER-METAL LAYER 0, AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide an integrated circuit comprising a structure where an inter-line capacitance is reduced, and to provide a manufacturing method for an integrated circuit wherein an impurity is prevented from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. SOLUTION: A cap layer or barrier layer which prevents an impurity from moving in a low permittivity material prevents the impurity from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. Related to an integrated circuit, a diffusion preventive barrier layer is deposited between a first dielectrics layer and a conductive layer above the integrated circuit. The diffusion-preventive barrier layer is the next metal layer which is formed, on the spot, at the dielectrics layer comprising impurity, and further, a process including polishing is performed with a multi-layer dielectrics structure. The on-the-spot deposition at the cap layer or barrier layer prevents a layer comprising impurities from being exposed to an atmosphere, and the cap layer or barrier layer prevents the layer from being contaminated with water content, hydrogen, etc.