SEMICONDUCTOR PACKAGE, AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To provide the manufacture of a wafer-level chip scale package, using a rewiring board. SOLUTION: This manufacture includes a stage of providing a rewiring board 130 which has a board foundation layer, a plurality of terminal pads 116 provided on that board foundation layer, a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KEN YOKAN, KYO SHIIN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide the manufacture of a wafer-level chip scale package, using a rewiring board. SOLUTION: This manufacture includes a stage of providing a rewiring board 130 which has a board foundation layer, a plurality of terminal pads 116 provided on that board foundation layer, a plurality of junction bumps 128, and a metallic wiring layer 122 for severally connecting the junction bumps 128 to the terminal pads 116, a step of joining a semiconductor wafer 100 provided with a plurality of integrated circuits and a plurality of chip bands 104 to the rewiring board 130, such that the junction bumps 128 of the rewiring board 130 contact with the chip pads 104 of the semiconductor wafer 100, a step of forming a plurality of external connection terminals 136 at each terminal pad 116 of the rewiring board 130, and a step of cutting the semiconductor wafer 100 and the rewiring board 130 so as to get individual semiconductor packages.