COMPRESSED AUDIO SIGNAL DECODER AND DECODER BUILT-IN RECEIVER

PROBLEM TO BE SOLVED: To reduce combinations of frames where discontinuous points are generated in a transition period when two frames different in encoding parameter such as frame length are successively inputted by performing a pipeline process, frame by frame, by using two DSPs. SOLUTION: A PCM o...

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Bibliographische Detailangaben
Hauptverfasser: NAKAMURA HIROSHI, SHIRANE HIROAKI, YAMAMOTO EIJI, OBATA SHINICHI, FUJII YUKIO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce combinations of frames where discontinuous points are generated in a transition period when two frames different in encoding parameter such as frame length are successively inputted by performing a pipeline process, frame by frame, by using two DSPs. SOLUTION: A PCM output I/F circuit 3 reads PCM output data that a DSP2 has stored out of a memory 7 as a time-series sample and a clock synchronized with an obtained sampling clock out of a PLL circuit 803. After the read of data from the memory 7 is controlled with a. parameter status signal ps2 and frame pulses, the data are supplied to a D/A converter 4 operating with the clock. The D/A converter 4 converts a PCM sample into an analog audio signal and sends it to an output terminal 10. A timing control circuit 8 is arranged so that the DSP1, DSP2, and PCM output I/F circuit 3 performs a pipeline process on the time base.