FLASH MEMORY DEVICE

PROBLEM TO BE SOLVED: To reduce a power noise or unwanted power consumption generated during state reading operation by previously generating a state data signal related to the state reading operation before a cycle for outputting the signal. SOLUTION: When a flag signal STATUS-EN is high, transmiss...

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Hauptverfasser: SAI KIKAN, BOKU SHOBIN
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce a power noise or unwanted power consumption generated during state reading operation by previously generating a state data signal related to the state reading operation before a cycle for outputting the signal. SOLUTION: When a flag signal STATUS-EN is high, transmission gates TG3 and TG4 are respectively deactivated and activated. At such a time, a state data signal SDS outputted by a state data signal generator 220 is inputted through the transmission gate TG4 to gates G6 and G7. When a second enable signal POE is high, corresponding to the logic level of an output signal, namely, the state data signal SDS from a selector 240, racing of pull-up to high or pull-down to low is generated in outputs DQ2 and DQ6. For solving this racing, the state data signal SDS to be outputted in the Nth cycle of an output enable signal OE# is previously generated in the (N-1)th cycle of the signal OE#. Therefore, the power noise or unwanted power consumption is prevented.