SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME
PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data fr...
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| creator | MANO RYUJI |
| description | PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data from a register circuit 12 is decided by a code decision circuit 14 and a signal Rsig indicating the decision result is outputted to a decode circuit 18. Also, output data of a 2 bit left shift circuit 13 and a 1 bit right shift circuit 15 are received at an absolute value comparator 17a, their absolute values are compared to each other, output data of a 2 bit left shift circuit 13 and an addition circuit 16 are received by an absolute value comparator 17b, their absolute values are compared and output data of a comparison result are outputted to the decode circuit 18. In the decode circuit 18, a quotient digit is decided according to a code decision circuit 14 and output signals of the absolute value comparators 17a and 17b. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2000298576A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2000298576A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2000298576A3</originalsourceid><addsrcrecordid>eNrjZNAODnUKCXJ0DvH0c1dwcQ3zdHZVcPRzUXD2DHIO9QxRcPMPUgjxcFUIdvR15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGBkaWFqbmZo7GRCkCAKLLJR4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME</title><source>esp@cenet</source><creator>MANO RYUJI</creator><creatorcontrib>MANO RYUJI</creatorcontrib><description>PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data from a register circuit 12 is decided by a code decision circuit 14 and a signal Rsig indicating the decision result is outputted to a decode circuit 18. Also, output data of a 2 bit left shift circuit 13 and a 1 bit right shift circuit 15 are received at an absolute value comparator 17a, their absolute values are compared to each other, output data of a 2 bit left shift circuit 13 and an addition circuit 16 are received by an absolute value comparator 17b, their absolute values are compared and output data of a comparison result are outputted to the decode circuit 18. In the decode circuit 18, a quotient digit is decided according to a code decision circuit 14 and output signals of the absolute value comparators 17a and 17b.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001024&DB=EPODOC&CC=JP&NR=2000298576A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001024&DB=EPODOC&CC=JP&NR=2000298576A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MANO RYUJI</creatorcontrib><title>SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME</title><description>PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data from a register circuit 12 is decided by a code decision circuit 14 and a signal Rsig indicating the decision result is outputted to a decode circuit 18. Also, output data of a 2 bit left shift circuit 13 and a 1 bit right shift circuit 15 are received at an absolute value comparator 17a, their absolute values are compared to each other, output data of a 2 bit left shift circuit 13 and an addition circuit 16 are received by an absolute value comparator 17b, their absolute values are compared and output data of a comparison result are outputted to the decode circuit 18. In the decode circuit 18, a quotient digit is decided according to a code decision circuit 14 and output signals of the absolute value comparators 17a and 17b.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAODnUKCXJ0DvH0c1dwcQ3zdHZVcPRzUXD2DHIO9QxRcPMPUgjxcFUIdvR15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGBkaWFqbmZo7GRCkCAKLLJR4</recordid><startdate>20001024</startdate><enddate>20001024</enddate><creator>MANO RYUJI</creator><scope>EVB</scope></search><sort><creationdate>20001024</creationdate><title>SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME</title><author>MANO RYUJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000298576A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MANO RYUJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MANO RYUJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME</title><date>2000-10-24</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data from a register circuit 12 is decided by a code decision circuit 14 and a signal Rsig indicating the decision result is outputted to a decode circuit 18. Also, output data of a 2 bit left shift circuit 13 and a 1 bit right shift circuit 15 are received at an absolute value comparator 17a, their absolute values are compared to each other, output data of a 2 bit left shift circuit 13 and an addition circuit 16 are received by an absolute value comparator 17b, their absolute values are compared and output data of a comparison result are outputted to the decode circuit 18. In the decode circuit 18, a quotient digit is decided according to a code decision circuit 14 and output signals of the absolute value comparators 17a and 17b.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME |
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