SUBTRACTING DEVICE AND CIRCUIT FOR THE SAME

PROBLEM TO BE SOLVED: To perform dividing operation at a high speed according to a division algorithm by deciding a quotient digit by third numerical data of first numerical data according to first and second comparison means and an output signal of a code decision means. SOLUTION: A code of data from a register circuit 12 is decided by a code decision circuit 14 and a signal Rsig indicating the decision result is outputted to a decode circuit 18. Also, output data of a 2 bit left shift circuit 13 and a 1 bit right shift circuit 15 are received at an absolute value comparator 17a, their absolute values are compared to each other, output data of a 2 bit left shift circuit 13 and an addition circuit 16 are received by an absolute value comparator 17b, their absolute values are compared and output data of a comparison result are outputted to the decode circuit 18. In the decode circuit 18, a quotient digit is decided according to a code decision circuit 14 and output signals of the absolute value comparators 17a and 17b.