FREQUENCY SYNTHESIZER

PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pu...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MINAGAWA AKIRA, NOSAKA HIDEYUKI
Format: Patent
Sprache:eng
Schlagworte:
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