FREQUENCY SYNTHESIZER

PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pulse at every pulse output of a pulse width adjusting circuit 29 into two distribution overflow signals. Delay generators 4 and 5 as delay generators are used and the distribution overflow signals are outputted to them. The first delay generator 4 inputs the first distribution overflow signal and delay time data which a data conversion circuit 2 outputs, sets the first distribution overflow signal as a trigger and outputs the pulse after timing following delay time data. The second delay generator 5 inputs the second distribution overflow signal and delay time data which the data conversion circuit 2 outputs, sets the second distribution overflow signal as the trigger and outputs the pulse after timing following delay time data.