FREQUENCY SYNTHESIZER
PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pu...
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| creator | MINAGAWA AKIRA NOSAKA HIDEYUKI |
| description | PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pulse at every pulse output of a pulse width adjusting circuit 29 into two distribution overflow signals. Delay generators 4 and 5 as delay generators are used and the distribution overflow signals are outputted to them. The first delay generator 4 inputs the first distribution overflow signal and delay time data which a data conversion circuit 2 outputs, sets the first distribution overflow signal as a trigger and outputs the pulse after timing following delay time data. The second delay generator 5 inputs the second distribution overflow signal and delay time data which the data conversion circuit 2 outputs, sets the second distribution overflow signal as the trigger and outputs the pulse after timing following delay time data. |
| format | Patent |
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SOLUTION: A pulse distribution circuit 3 distributes a pulse at every pulse output of a pulse width adjusting circuit 29 into two distribution overflow signals. Delay generators 4 and 5 as delay generators are used and the distribution overflow signals are outputted to them. The first delay generator 4 inputs the first distribution overflow signal and delay time data which a data conversion circuit 2 outputs, sets the first distribution overflow signal as a trigger and outputs the pulse after timing following delay time data. The second delay generator 5 inputs the second distribution overflow signal and delay time data which the data conversion circuit 2 outputs, sets the second distribution overflow signal as the trigger and outputs the pulse after timing following delay time data.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; GENERATION OF NOISE BY SUCH CIRCUITS ; GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER ; PULSE TECHNIQUE</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001006&DB=EPODOC&CC=JP&NR=2000278048A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001006&DB=EPODOC&CC=JP&NR=2000278048A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MINAGAWA AKIRA</creatorcontrib><creatorcontrib>NOSAKA HIDEYUKI</creatorcontrib><title>FREQUENCY SYNTHESIZER</title><description>PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pulse at every pulse output of a pulse width adjusting circuit 29 into two distribution overflow signals. Delay generators 4 and 5 as delay generators are used and the distribution overflow signals are outputted to them. The first delay generator 4 inputs the first distribution overflow signal and delay time data which a data conversion circuit 2 outputs, sets the first distribution overflow signal as a trigger and outputs the pulse after timing following delay time data. The second delay generator 5 inputs the second distribution overflow signal and delay time data which the data conversion circuit 2 outputs, sets the second distribution overflow signal as the trigger and outputs the pulse after timing following delay time data.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>GENERATION OF NOISE BY SUCH CIRCUITS</subject><subject>GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB1C3INDHX1c45UCI70C_FwDfaMcg3iYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgYGRuYWBiYWjsZEKQIA9a4fqA</recordid><startdate>20001006</startdate><enddate>20001006</enddate><creator>MINAGAWA AKIRA</creator><creator>NOSAKA HIDEYUKI</creator><scope>EVB</scope></search><sort><creationdate>20001006</creationdate><title>FREQUENCY SYNTHESIZER</title><author>MINAGAWA AKIRA ; NOSAKA HIDEYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000278048A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>GENERATION OF NOISE BY SUCH CIRCUITS</topic><topic>GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>MINAGAWA AKIRA</creatorcontrib><creatorcontrib>NOSAKA HIDEYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MINAGAWA AKIRA</au><au>NOSAKA HIDEYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FREQUENCY SYNTHESIZER</title><date>2000-10-06</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To remove the limit of the output frequency of a frequency synthesizer by means of the finiteness of reset time and to generate the output frequency to a clock frequency by sequentially operating plural delay generators. SOLUTION: A pulse distribution circuit 3 distributes a pulse at every pulse output of a pulse width adjusting circuit 29 into two distribution overflow signals. Delay generators 4 and 5 as delay generators are used and the distribution overflow signals are outputted to them. The first delay generator 4 inputs the first distribution overflow signal and delay time data which a data conversion circuit 2 outputs, sets the first distribution overflow signal as a trigger and outputs the pulse after timing following delay time data. The second delay generator 5 inputs the second distribution overflow signal and delay time data which the data conversion circuit 2 outputs, sets the second distribution overflow signal as the trigger and outputs the pulse after timing following delay time data.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY GENERATION OF NOISE BY SUCH CIRCUITS GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER PULSE TECHNIQUE |
| title | FREQUENCY SYNTHESIZER |
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