METHOD FOR STRUCTURING LOGICAL CONFIGURATION BY USING ELECTRICALLY RECONFIGURABLE GATE ARRAY

PROBLEM TO BE SOLVED: To actualize the method for structuring a logical configuration by using the electrically reconfigurable gate array. SOLUTION: Electrically reconfigurable gate array(ERCGA) logic chips are connected to one another via reconfigurable interconnections. The electrical representati...

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Bibliographische Detailangaben
Hauptverfasser:	BUTTS MICHAEL R, BATCHELLER JON A
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING
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Zusammenfassung:	PROBLEM TO BE SOLVED: To actualize the method for structuring a logical configuration by using the electrically reconfigurable gate array. SOLUTION: Electrically reconfigurable gate array(ERCGA) logic chips are connected to one another via reconfigurable interconnections. The electrical representation of a large-scale digital network is so converted as to adopt a hardware style which operates actually and temporarily on the interoconnected chips. The digital network actualized on the interconnected chips can be changed any time through reconfigured connections. Consequently, a system is adapted to various purposes including simulation, prototyping, execution, and computation. The reconfigurable interconnections are configured by the ERCGA chips dedicated to an interconnecting function. Each interconnected ERCGAs is not connected to all the interconnected chips, but at least one pin.