INTEGRATED CIRCUIT ELEMENT HAVING FLAT INTER-LEVEL DIELECTRIC LAYER

PROBLEM TO BE SOLVED: To provide an integrated circuit element, having a planarized inter- level dielectric layer with a low permittivity (K) containing an FSG layer of which conductive layer is protected from exposure to fluorine. SOLUTION: This integrated circuit 28 contains a conductive layer adj...

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Bibliographische Detailangaben
Hauptverfasser:	ABDELGADIR MAHJOUB ALI, ALVARO MAURY
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY SEMICONDUCTOR DEVICES SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide an integrated circuit element, having a planarized inter- level dielectric layer with a low permittivity (K) containing an FSG layer of which conductive layer is protected from exposure to fluorine. SOLUTION: This integrated circuit 28 contains a conductive layer adjacent to a semiconductor substrate 30. The conductive layer contains conductive wires having gaps therebetween. A fluorine-silicate glass(FSG) layer covers a patterned conductive layer and fills the gaps between the conductive wires. An undoped oxide layer 38 exists on an FSG layer 36. The peak of the FSG layer 36 covering the conductive metal wires is reduced through CMP. Thus, the FSG film 36 of the following conductive layer is substantially protected from exposure to fluorine.