SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To reduce the interference noise between bit line pair by adjacently arranging each bit line constituting a paired bit line so that no pattern is present between them, and providing other pattern between adjoining bit paired lines. SOLUTION: Bit lines BLT and BLB of a bit paired line BL are sequentially and electrically connected to an I/O switch circuit I/O SW, etc., through a shared circuit SHA. Shared circuits SHA and SHB comprise a function for electrically connecting or disconnecting the bit lines BLT and BLB of a memory region M from those of a peripheral circuit region P, while configuring an n-channel type MISFET (nMISQ SHN). One of a source/drain semiconductor region of the nMISQ SHN is electrically connected to bit lines BLT and BLB 2 of the memory region M while the other is connected to the bit lines BLT and BLB of the peripheral circuit region P. The nMISQ SHN is on/off controlled by the signal inputted to its gate electrode.