CENTRAL PROCESSING UNIT HAVING EXTENDED INSTRUCTION WORD

PROBLEM TO BE SOLVED: To simplify an instruction word decoder circuit by using a fixed length instruction word and to provide a central processing unit easy in exception processing and simple in a pipeline and a memory management device by storing the value of a program counter(PC) and the value of a state register in a stack area. SOLUTION: The value of the PC and the value of the state register are stored in the stack area. In this unit, when reset is performed first, a starting address is read from a memory and stored in a data latch part 10 and the value is stored in a PC counter inside a register file 80. The value is referred to in an address generation part 90 and respective programs intended by a user are read from the memory. Then, an instruction word for the pipeline is fetched to a pre instruction word register 20, the instruction word is latched to an instruction word register 40 thereafter and control signals corresponding to the respective states of the instruction word are generated. An arithmetic processing part 60 and a multiplier/divider 70 are operated by the control signals and a result is stored in the register file 80.