MEMORY CIRCUIT, THE MEMORY CIRCUIT AND OPERATION METHOD OF ELEMENT, REDUCTION METHOD FOR BIT-LINE CONTROL SWITCHING, AND BIT-LINE SELECTION CONTROLLER FOR REDUCING THE BIT-LINE CONTROL SWITCHING IN THE MEMORY CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which power consumption is reduced and its refreshing method. SOLUTION: A memory circuit comprises many memory cell arrays 100, a row of many bit line sensitive amplifiers 102 connected to the pair of adjacent memory cell array positioned between respective adjacent pair of memory cell arrays, and many bit line selection controllers 106 which have first bit-line selection control line respectively and which are connected to ore row of the bit-line sensitive amplifiers for controlling ore row of the many bit-line sensitive amplifiers, the first bit line selection control line is utilized for controlling connection between ore row of the bit line sensitive amplifier and are array of the pairs of adjacent memory cell array, the first bit-line selection control line which is switching turned on once is switched off only at the time of activation of other arrays out of the pairs of adjacent memory cell array.