WIRING BOARD AND ITS MANUFACTURING METHOD

WIRING BOARD AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a wiring board with improved suppression of short- circuiting failures, and its manufacturing method. SOLUTION: A wiring board is provided with a plurality of conductors 6 for terminal which are in parallel at the end part of a substrate 1, and is also provided with...

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Hauptverfasser: KUROKAWA HIROSHI, ISO TOSHIAKI, KOBAYASHI SHIGETAKA, OTSUKA OSAMU, OSAWA MASAYUKI
Format: Patent
Sprache:eng
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CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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creator KUROKAWA HIROSHI
ISO TOSHIAKI
KOBAYASHI SHIGETAKA
OTSUKA OSAMU
OSAWA MASAYUKI
description PROBLEM TO BE SOLVED: To provide a wiring board with improved suppression of short- circuiting failures, and its manufacturing method. SOLUTION: A wiring board is provided with a plurality of conductors 6 for terminal which are in parallel at the end part of a substrate 1, and is also provided with a conductor 3 to a first terminal, that is formed over an outer shape line 2 of the end part before subjecting it to shape machining and a conductor 4 for a second terminal, that is formed only on the inside from the outer shape line 2 of the end part. The conductor 3 for the first terminal and the conductor 4 for the second terminal are formed alternately.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2000183480A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2000183480A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2000183480A3</originalsourceid><addsrcrecordid>eNrjZNAM9wzy9HNXcPJ3DHJRcPRzUfAMCVbwdfQLdXN0DgkFy_m6hnj4u_AwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAwNDC2MTCwNHY6IUAQBlPSSo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING BOARD AND ITS MANUFACTURING METHOD</title><source>esp@cenet</source><creator>KUROKAWA HIROSHI ; ISO TOSHIAKI ; KOBAYASHI SHIGETAKA ; OTSUKA OSAMU ; OSAWA MASAYUKI</creator><creatorcontrib>KUROKAWA HIROSHI ; ISO TOSHIAKI ; KOBAYASHI SHIGETAKA ; OTSUKA OSAMU ; OSAWA MASAYUKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wiring board with improved suppression of short- circuiting failures, and its manufacturing method. SOLUTION: A wiring board is provided with a plurality of conductors 6 for terminal which are in parallel at the end part of a substrate 1, and is also provided with a conductor 3 to a first terminal, that is formed over an outer shape line 2 of the end part before subjecting it to shape machining and a conductor 4 for a second terminal, that is formed only on the inside from the outer shape line 2 of the end part. The conductor 3 for the first terminal and the conductor 4 for the second terminal are formed alternately.</description><edition>7</edition><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20000630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2000183480A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20000630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2000183480A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUROKAWA HIROSHI</creatorcontrib><creatorcontrib>ISO TOSHIAKI</creatorcontrib><creatorcontrib>KOBAYASHI SHIGETAKA</creatorcontrib><creatorcontrib>OTSUKA OSAMU</creatorcontrib><creatorcontrib>OSAWA MASAYUKI</creatorcontrib><title>WIRING BOARD AND ITS MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a wiring board with improved suppression of short- circuiting failures, and its manufacturing method. SOLUTION: A wiring board is provided with a plurality of conductors 6 for terminal which are in parallel at the end part of a substrate 1, and is also provided with a conductor 3 to a first terminal, that is formed over an outer shape line 2 of the end part before subjecting it to shape machining and a conductor 4 for a second terminal, that is formed only on the inside from the outer shape line 2 of the end part. The conductor 3 for the first terminal and the conductor 4 for the second terminal are formed alternately.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAM9wzy9HNXcPJ3DHJRcPRzUfAMCVbwdfQLdXN0DgkFy_m6hnj4u_AwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAwNDC2MTCwNHY6IUAQBlPSSo</recordid><startdate>20000630</startdate><enddate>20000630</enddate><creator>KUROKAWA HIROSHI</creator><creator>ISO TOSHIAKI</creator><creator>KOBAYASHI SHIGETAKA</creator><creator>OTSUKA OSAMU</creator><creator>OSAWA MASAYUKI</creator><scope>EVB</scope></search><sort><creationdate>20000630</creationdate><title>WIRING BOARD AND ITS MANUFACTURING METHOD</title><author>KUROKAWA HIROSHI ; ISO TOSHIAKI ; KOBAYASHI SHIGETAKA ; OTSUKA OSAMU ; OSAWA MASAYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000183480A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>KUROKAWA HIROSHI</creatorcontrib><creatorcontrib>ISO TOSHIAKI</creatorcontrib><creatorcontrib>KOBAYASHI SHIGETAKA</creatorcontrib><creatorcontrib>OTSUKA OSAMU</creatorcontrib><creatorcontrib>OSAWA MASAYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUROKAWA HIROSHI</au><au>ISO TOSHIAKI</au><au>KOBAYASHI SHIGETAKA</au><au>OTSUKA OSAMU</au><au>OSAWA MASAYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING BOARD AND ITS MANUFACTURING METHOD</title><date>2000-06-30</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wiring board with improved suppression of short- circuiting failures, and its manufacturing method. SOLUTION: A wiring board is provided with a plurality of conductors 6 for terminal which are in parallel at the end part of a substrate 1, and is also provided with a conductor 3 to a first terminal, that is formed over an outer shape line 2 of the end part before subjecting it to shape machining and a conductor 4 for a second terminal, that is formed only on the inside from the outer shape line 2 of the end part. The conductor 3 for the first terminal and the conductor 4 for the second terminal are formed alternately.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title WIRING BOARD AND ITS MANUFACTURING METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T04%3A46%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KUROKAWA%20HIROSHI&rft.date=2000-06-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2000183480A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true