SYNCHRONIZATION TYPE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH WAVE PIPELINE SCHEME AND DATA BUS CONTROL METHOD THEREFOR

PROBLEM TO BE SOLVED: To enhance the performance and to increase an operating frequency by storing read data corresponding to an in-th clock cycle to a corresponding latch circuit synchronously with a clock signal of an (i+1)-th clock cycle. SOLUTION: Since a registration input control signal having...

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Bibliographische Detailangaben

1. Verfasser:	KIN NANSHO
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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