SYNCHRONIZATION TYPE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH WAVE PIPELINE SCHEME AND DATA BUS CONTROL METHOD THEREFOR

PROBLEM TO BE SOLVED: To enhance the performance and to increase an operating frequency by storing read data corresponding to an in-th clock cycle to a corresponding latch circuit synchronously with a clock signal of an (i+1)-th clock cycle. SOLUTION: Since a registration input control signal having been activated in a preceding clock cycle is kept to a switch-on state in a present clock cycle, a switch circuit of a register 280 is kept to a switch-on state and a latch circuit latches output data of a data line sensing amplifier circuit 260. A register input control circuit 320 inactivates a high level control signal into a low level synchronously with a leading edge of a clock signal and activates a succeeding control signal to a high level. That is, the control signal is synchronously with an external clock signal that is equivalent to a clock cycle delayed by about one clock cycle on the basis of the clock cycle.