SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To hold a bus line at an intermediate potential, without allowing a through-current, which flows between a power source and the GND, to flow. SOLUTION: When a high pulse is outputted as an internal pulse signal RBEQ while a read bus line RB is in a low state, an N-type transist...

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Bibliographische Detailangaben
Hauptverfasser: YAMADA YUKINORI, UCHIDA SHOZO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To hold a bus line at an intermediate potential, without allowing a through-current, which flows between a power source and the GND, to flow. SOLUTION: When a high pulse is outputted as an internal pulse signal RBEQ while a read bus line RB is in a low state, an N-type transistor(TR) N2 and a P-type TR, P2 are turned on. An N-type TR N5 also turns on. An N-type TR N3 turns off, and an N type TR N4 turns on, and P type transistors P3 and P4 also turn on. Consequently, the output of an inverter I2 goes down to a low level, a P type TR P1 turns on, and an N-type TR N1 turns off, so that the potential of the read bus line RB varies from the low level to the high level. When the signal RBEWQ is held at the low level, the P type TR P2 and N type TR N2 turn off and the read bus line RB is held at the intermediate potential level.