SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To minimize the expansion of a chip size by bringing a first electrode into contact with the partial upper surface of a capacitor formation film simultaneously with a capacitor for circuit for a capacitor for detecting failure, at the same time bringing an isolation layer into...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To minimize the expansion of a chip size by bringing a first electrode into contact with the partial upper surface of a capacitor formation film simultaneously with a capacitor for circuit for a capacitor for detecting failure, at the same time bringing an isolation layer into contact with a lower surface, and providing a second electrode for leading the layer. SOLUTION: After an insulation film 6 at the upper portion of one portion 1a of an isolation layer is punched, a capacitor formation film 3 for forming a capacitor for circuit is provided on the entire surface of a wafer, and at the same time aluminum wiring 5a that is a first electrode is formed on the capacitor formation film 3 at the hole part. Also, the insulation film 6 at the upper portion of one portion 1b of the isolation layer and a capacitor formation film are punched, and aluminum wiring 5b that is a second electrode for leading the isolation layer is executed to cover its one portion for forming as a test pad at its one portion, thus incorporating a capacitor for detecting the failure of the capacitor formation film 3 in the same chip. |
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