FLASH MEMORY DEVICE AND ITS VERIFYING METHOD
PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage performing stable verifying sense operation. SOLUTION: The word line voltage supply circuit of the nonvolatile semiconductor memory device reduces a power source noise by inactivating a high voltage generator 52 during the verifyin...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage performing stable verifying sense operation. SOLUTION: The word line voltage supply circuit of the nonvolatile semiconductor memory device reduces a power source noise by inactivating a high voltage generator 52 during the verifying sense operation. The word line voltage supply circuit contains the high voltage generator 52 generating a high voltage signal according to a control signal outputted from a controller 58. A voltage regulator 54 adjusts the high voltage signal to generate a verifying voltage signal applied to a selected memory cell. The controller 58 inactivates the control signal during the verifying sense operation for removing the power source noise occurring due to the pumping operation of the high voltage generator 52. |
---|