CLOCK CONTROL CIRCUIT AND DIGITAL SIGNAL PROCESSOR

PROBLEM TO BE SOLVED: To provide a clock control circuit capable of changing over clocks without substantially imparting hindrance on places where clocks are to be supplied. SOLUTION: This circuit is provided with a clock generating part 101 which changes over at least clocks having two frequencies to output the changed over clock as a master clock 209 and a timing control part 102 outputting output clocks 207, 208 based on the master clock 209. When the timing control part 102 receives a clock changeover request, the part 102 monitors access information signal 202 with respect to the output clocks 207, 208 and instructs the changeover of the master clock 209 to a clock generating part 101 in a timing when access to the output clocks 207, 208 is not present.